1. Field
Example embodiments relate to semiconductor memory devices and methods of manufacturing the semiconductor memory device. Other example embodiments relate to semiconductor memory devices that perform an erase operation using an erase gate and methods of manufacturing the semiconductor memory device.
2. Description of the Related Art
A non-volatile memory device, which electrically erases and programs data, preserves stored data even when no supply voltage is applied thereto. A non-volatile memory device is, for example, a flash memory.
Each of a plurality of memory cells constituting a flash memory includes a cell transistor with a control gate, a floating gate, a source and a drain. Program or erase operations may be performed in the cell transistor using a Fowler-Nordheim (F-N) tunneling mechanism. However, the size of the floating gate is limited to the reduction in the size of the flash memory.
In order to overcome the size limitation of the floating gate, a non-volatile memory device (hereinafter referred to as a “charge trap memory device”) including a charge trap layer instead of a floating gate has been developed. The charge trap memory device stores electrons in the charge trap layer. The charge trap memory device may be smaller than a conventional non-volatile memory device that stores electrons in a floating gate.
In a conventional charge trap memory device, as program and erase operations are repeated, an interface trap and an oxide trap may form. In more detail, if the conventional charge trap memory device is in an erase mode, a high voltage may be applied to a semiconductor substrate of the device. A plurality of holes may be injected into the charge trap layer from the semiconductor substrate such that electrons stored in the charge trap layer are removed.
In this case, silicon-hydrogen (Si—H) bonds that exist in the interface between the semiconductor substrate and a polysilicon layer are broken and an interface trap may form between the semiconductor substrate and the polysilicon layer. Hydrogen (H) elements caused by the breaking of the Si—H bonds are moved (or migrate) inside the polysilicon layer and form an oxide trap. As such, the reliability of the charge trap memory device deteriorates.
A structure having components arranged on an insulation layer (e.g., a Thin Film Transistor (TFT) or Silicon On Insulator (SOI)) may be used. As described above, if a conventional charge trap memory device is in an erase mode, a high voltage may be applied to a semiconductor substrate of the device.